1. Field of the Invention
The present invention relates to a head element substrate, a recording head, and a recording apparatus. More particularly, the present invention relates to a head element substrate which has an electrothermal transducer for generating the heat energy necessary to record an image and a drive circuit for driving the electrothermal transducer formed on the same substrate, a recording head provided with the head element substrate, and a printing apparatus using the recording head.
2. Description of the Related Art
For an inkjet recording apparatus, a recording head including a discharge port and an electrothermal transducer which generates discharge energy for discharging ink from the discharge port as a recording element is known. Such a recording apparatus records an image by discharging ink based on the desired recording information.
As the configuration of the recording head of an inkjet recording apparatus, a recording head provided with a plurality of recording elements in one array or in a plurality of arrays has conventionally been known. Generally, the recording elements in such a recording head and the drive circuits thereof are formed on the same substrate using semiconductor fabrication process technology.
As a method for driving a recording head, time-division driving is practically used. Since there is an upper limit on the maximum consumed power which can simultaneously drive the recording elements, time-division driving is employed in which a plurality of recording elements are divided into M blocks formed from N recording elements, and N recording elements are simultaneously driven per block. This driving method will now be described with a specific circuit configuration employed in time-division driving.
FIG. 16 is an equivalent circuit diagram of a conventional head element substrate. A head element substrate 100 includes a data terminal, a clock terminal, a latch terminal, and a heat signal terminal. Further, the following features are built into the head element substrate 100 as a drive circuit 103: a shift register 21 for holding recording data and block control data; a latch circuit 22 which latches the held data; an AND circuit 23 which calculates the logical product of an output signal from the latch circuit and a signal from a heat signal terminal; a decoder 24 which outputs a signal for selecting a block; an AND circuit 25 which selects a recording element 27 to be driven; a switching element 26 for driving the recording element and the like. In a recording element array 102, recording elements are arranged in line, sharing a power source VH and GND with one another.
Data in which recording data and block control data are serially combined is input from the data terminal, and a clock for transferring the data is input from the clock terminal into the drive circuit 103 respectively. Further, from the latch terminal, a latch signal which latches data held in the shift register 21 is input, and from the heat signal terminal, a heat signal as a drive pulse width signal which defines the power-on period of a recording element, is input into the drive circuit 103.
FIG. 17 illustrates a timing chart representing the communication state of the drive circuit 103. As illustrated in FIG. 17, in the present specification, the period from data transfer start of a first block to data transfer start of the next first block is referred to as a “drive period”. Further, the period from data transfer start of a first block to data transfer start of a second block in the same drive period is referred to as a “block period”. Data corresponding to one block of recording elements is transferred per block period, and data corresponding to one array of recording elements is transferred in one drive period.
The data (DATA) of the first block is input into the shift register 21 by a clock (CLK). Then, based on the latch signal (LAT), recording data and block control data held in the shift register 21 are output from the latch circuit 22. The logical product of the recording data of the first block output from the latch circuit 22 and the heat signal (HEAT) which is input while the data of the second block is being transferred is calculated by the AND circuit 23. On the other hand, the block control data of the first block is input into the decoder 24, and based on that input, a block selection signal BLE is output from the decoder. The logical product of this block selection signal BLE and the output signal of the AND circuit 23 is calculated by the AND circuit 25. If that output signal is active, the switching element 26, which is a MOS transistor or the like, is selected and driven. A recording operation is thus performed by selecting a recording element corresponding to the recording data and the block control data, and energizing the recording element to discharge ink from a nozzle. This operation is repeated from the first block to the Mth block to record one array of a recording element.
Further, with respect to a recording head mounted with a head element substrate, a recording head provided with one array of recording elements, or a plurality of arrays of recording elements has conventionally been known. In such a recording head, with N recording elements as one block, multiple or several tens of drive circuits which can be simultaneously driven are mounted on the same head element substrate. By arraying recording data so as to correspond to a respective recording element, inputting the recording data into the recording head, and driving the recording elements, arbitrary recording can be performed on a recording medium such as recording paper.
Recording head performance has dramatically improved in recent years while the precision is increased and the image quality is improved. On the other hand, along with this increased precision and improved image quality, the number of recording elements has grown, or the number of simultaneous drives of the recording elements has grown in order to improve the recording rate. As a result, the number of connection terminals between the recording head and the recording apparatus main unit has increased, which has led to various problems such as an increase in the cost of the connector unit between the recording head and the recording apparatus main unit, and contact point defects in the connection portion.
As a method for reducing the number of connection terminals, in U.S. Pat. No. 6,830,301, the number of connection terminals is reduced by commonly inputting the recording data of a plurality of blocks and drive pulse width signals from the recording apparatus main unit into the recording head.
Further, as a method for utilizing a plurality of input pulses as a large variety of pulses, U.S. Pat. No. 6,116,714 discusses a method for selecting a plurality of input pulses to form a plurality of heat pulses.
Further, since the number of recording elements is increasing due to the increased precision and improved image quality, the block division number in the above-described time-division driving is tending to increase. If the block period is fixed, the drive period will become longer due to the increase of the block division number.
In the future, there will be further a need for improvements in speed. Therefore, especially in recording apparatuses, along with the increase in the number of recording elements, the transfer of increasing amounts of recording information at high speed via a small number of terminals will be an important challenge.
FIG. 5 of U.S. Pat. No. 7,029,084 illustrates a data low-voltage differential signaling (LVDS) transmission line of a clock and data wired from a recording apparatus to a drive circuit in a recording head. More specifically, in this configuration, a serial data stream and a clock corresponding thereto are received by the LVDS line. LVDS technology is effective for high-speed transfer and also as a measure against noise, and is thus effective in a recording head.
U.S. Pat. No. 6,830,301 discusses a following data transfer method. As illustrated in FIG. 18, a plurality of blocks of recording data and block control data (DATA), and a drive pulse width signal (ENB signal, corresponding to HEAT) are serially transferred to the gate array of a carriage using a common signal line. As a result, the block period becomes longer and the problem of a longer drive period appears. In such a configuration, how to deal with the increase in speed which will be demanded even more in the future becomes a challenge.